GXM Datasheet, PDF (70/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Processor Programming (Continued)
3.8 MULTITASKING AND TASK STATE SEGMENTS
The CPU enables rapid task switching using JMP and During task switching, the processor saves the current
CALL instructions that refer to Task State Segments CPU state in the TSS before starting a new task. The TSS
(TSS). During a switch, the complete task state of the cur- can be either a 386/486-type 32-bit TSS (see Table 3-26) or a
rent task is stored in its TSS, and the task state of the 286-type 16-bit TSS (see Table 3-27 on page 71).
requested task is loaded from its TSS. The TSSs are
defined through special segment descriptors and gates.
Task Gate Descriptors. A task gate descriptor provides
controlled access to the descriptor for a task switch. The
The Task Register (TR) holds 16-bit descriptors that con- DPL of the task gate is used to control access. The selec-
tain the base address and segment limit for each task tor’s RPL and the CPL of the procedure must be a higher
state segment. The TR is loaded and stored via the LTR level (numerically less) than the DPL of the descriptor.
and STR instructions, respectively. The TR can only be The RPL in the task gate is not used.
accessed only during protected mode and can be loaded
when the privilege level is 0 (most privileged). When the
TR is loaded, the TR selector field indexes a TSS descrip-
tor that must reside in the Global Descriptor Table (GDT).
The I/O Map Base Address field in the 32-bit TSS points
to an I/O permission bit map that often follows the TSS at
location +68h.
Only the 16-bit selector of a TSS descriptor in the TR is
accessible. The BASE, TSS LIMT and ACCESS RIGHT
fields are program invisible.
Table 3-26. 32-Bit Task State Segment (TSS) Table
31
16 15
0
I/O Map Base Address
000000000000000T
0000000000000000
Selector for Task’s LDT
0000000000000000
GS
0000000000000000
FS
0000000000000000
DS
0000000000000000
SS
0000000000000000
CS
0000000000000000
ES
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
0000000000000000
SS for CPL = 2
ESP for CPL = 2
0000000000000000
SS for CPL = 1
ESP for CPL = 1
0000000000000000
SS for CPL = 0
ESP for CPL = 0
0000000000000000
Back Link (Old TSS Selector)
Note: 0 = Reserved
+64h
+60h
+5Ch
+58h
+54h
+50h
+4Ch
+48h
+44h
+40h
+3Ch
+38h
+34h
+30h
+2Ch
+28h
+24h
+20h
+1Ch
+18h
+14h
+10h
+Ch
+8h
+4h
+0h
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