GXM Datasheet, PDF (31/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Signal Definitions (Continued)
2.2.4 Video Interface Signals (Continued)
Signal Name
BGA SPGA
Pin No Pin No
Type
CRT_VSYNC
AA3
AH2
O
FP_HSYNC
L2
R4
O
FP_VSYNC
J1
P2
O
ENA_DISP
AD5
AM6
O
VID_RDY
AD1
AK2
I
VID_VAL
M2
S3
O
VID_DATA[7:0]
Refer Refer
O
to
to Table
2-5
PIXEL[17:0]
Refer Refer
O
to Table to Table
2-3
2-5
Description
CRT Vertical Sync
CRT Vertical Sync establishes the screen refresh rate and verti-
cal retrace interval for an attached CRT. The polarity is program-
mable and depends on the display mode.
Flat Panel Horizontal Sync
Flat Panel Horizontal Sync establishes the line rate and horizon-
tal retrace interval for a TFT display. Polarity is programmable
and depends on the display mode.
This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.
If no flat panel is used in the system, this signal does not need to
be connected.
Flat Panel Vertical Sync
Flat Panel Vertical Sync establishes the screen refresh rate and
vertical retrace interval for a TFT display. Polarity is programma-
ble and depends on the display mode.
This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.
If no flat panel is used in the system, this signal does not need to
be connected.
Display Enable
Display Enable indicates the active display portion of a scan line
to the CS5530.
In a CS5530-based system, this signal is required to be con-
nected even if there is no TFT panel in the system.
Video Ready
This input signal indicates that the video FIFO in the CS5530 is
ready to receive more data.
Video Valid
VID_VAL qualifies valid video data to the CS5530.
Video Data Bus
When the Video Port is enabled, this bus drives Video (Y-U-V)
data synchronous to the VID_CLK output.
Graphics Pixel Data Bus
This bus drives graphics pixel data synchronous to the PCLK
output.
Revision 3.1
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