GXM Datasheet, PDF (44/244 Pages) National Semiconductor (TI) – Geode™ GXm Processor Integrated x86 Solution with MMX Support

Processor Programming (Continued)
3.3.2 System Register Set
The system register set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level
programmers who generate operating systems and mem-
ory management programs. Associated with the system
register set are certain tables and segments which are
listed in Table 3-5.
The Control Registers control certain aspects of the
GXm processor such as paging, coprocessor functions,
and segment protection.
The Descriptor Tables hold descriptors that manage
memory segments and tables, interrupts and task switch-
ing. The tables are defined by corresponding registers.
The two Task State Segments Tables defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.
The Configuration Registers are used to define the
GXm CPU setup including cache management.
The ID registers allow BIOS and other software to identify
the specific CPU and stepping. System Management
Mode (SMM) control information is stored in the SMM reg-
isters.
The Debug Registers provide debugging facilities for the
GXm processor and enable the use of data access break-
points and code execution breakpoints.
The Test Registers provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB). The TLB is used as a cache for
the tables that are used in to translate linear addresses to
physical addresses while paging is enabled.
Table 3-5 lists the system register sets along with their
size and function.
Table 3-5. System Register Set
Group
Control
Registers
Name
CR0
CR2
CR3
Descriptor
Tables
CR4
GDT
IDT
Descriptor
Table
Registers
Task State
Segment and
Registers
Configuration
Registers
ID
Registers
SMM
Registers
Performance
Registers
Debug
Registers
LDT
GDTR
IDTR
LDTR
TSS
TR
CCRn
DIRn
SMARn
SMHRn
PCR0
DR0
DR1
DR2
DR3
Test
Registers
DR6
DR7
TR3
TR4
TR5
TR6
TR7
Function
System Control
Register
Page Fault Linear
Address Register
Page Directory Base
Register
Time Stamp Counter
General Descriptor Table
Interrupt Descriptor
Table
Local Descriptor Table
GDT Register
IDT Register
LDT Register
Task State Segment
Tables
TSS Register Setup
Configuration Control
Registers
Device Identification
Registers
SMM Address Region
Registers
SMM Header Addresses
Performance Control
Register
Linear Breakpoint
Address 0
Linear Breakpoint
Address 1
Linear Breakpoint
Address 2
Linear Breakpoint
Address 3
Breakpoint Status
Breakpoint Control
Cache Test
Cache Test
Cache Test
TLB Test Control
TLB Test Status
Width
(Bits)
32
32
32
32
32
32
16
32
32
16
16
16
8
8
8
8
8
32
32
32
32
32
32
32
32
32
32
32
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