M16C Datasheet, PDF (72/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. Table 7-1 shows the DMAC specifications. Figure 7-1 shows the block
diagram of the DMAC. Figures 7-2 to 7-4 show the registers used by the DMAC.
Table 7-1. DMAC specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 byDMA1) or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
UART2 transmission and reception interrupt requests
Serial I/O3 interrupt request
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer
The DMA enable bit is cleared and transfer ends when an underflow
occurs in the transfer counter
• Repeat transfer
When an underflow occurs in the transfer counter, the value in the transfer counter
reload register is reloaded into the transfer counter and the DMA transfer is repeated
DMA interrupt request generation timing When an underflow occurs in the transfer counter
DMA startup
• Single transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
• Repeat transfer
Transfer starts when the DMA is requested after “1” is written to the DMA enable bit
Transfer starts when the DMA is requested after an underflow occurs in the transfer counter
DMA shutdown
• When “0” is written to the DMA enable bit
• When, in single transfer mode, an underflow occurs in the transfer counter
Forward address pointer and When DMA transfer starts, the value of whichever of the source or destination pointer
reload timing for transfer
that is set up as the forward pointer is reloaded into the forward address pointer. The
counter
value in the transfer counter reload register is reloaded into the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt.
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