M16C Datasheet, PDF (216/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMCR
Address
03B716
When reset
XX0000012
Bit symbol
Bit name
FMCR0 ^{RY/BY status flag}
Function
0: Busy (being written or erased)
1: Ready
RR WW
FMCR1 CPU rewrite mode
select bit (Note 2)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
FMCR2 ^{Lock bit disable bit}
(Note 3)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
FMCR3 ^{Flash memory reset bit 0: Normal operation}
(Note 3)
1: Reset
This bit must always be set to 0.
FMCR5 ^{User ROM area select bit ( 0: Boot ROM area is accessed}
Note 5) (Effective in only _{1: User ROM area is accessed}
boot mode)
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: The value of the flash memory control register after a reset is "--000001".
Note 2: For this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession. Use the control
program except in the internal flash memory for write to this bit.
Note 3: For this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession when the CPU
rewrite mode select bit = 1.
Note 4: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting
it to 1 (reset).
Note 5: Use the control program except in the internal flash memory for write to this bit.
Figure 23-1. Flash memory control register
Flash memory control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 00 00 00
Symbol
FMCR2
Address
03B616
When reset
XX0000012
Bit symbol
Bit name
Reserved bits
FMCR22 Flash memory power
supply-OFF bit (Note)
Reserved bits
Function
Must always be set to "0".
RR WW
0: Flash memory power supply
is connected.
1: Flash memory power supply-OFF
Must always be set to "0".
Note: For this bit to be set to "1", the user needs to write a 0"" and then a 1 to it in succession. When this
procedure is not taken, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA
transfer will be executed during the interval. During parallel I/O mode, programming, erase, or read
of flash memory is not controlled by this bit, only by external pins.
Figure 23-2. Flash memory control register 2
216