M16C Datasheet, PDF (164/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Wake Up Logic:
Interrupt Generation:
The MCU can be set to stop- or wait mode to reduce power consumption. This module
provides the possibility to wake up the MCU from sleep mode via the CAN bus (refer
to section CAN wake up interrupt).
The CAN module signals the CPU different events via 6 interrupts.
Four interrupt channels are used for successful CAN message transmission and re-
ception indication, i.e. 'message receive successful' interrupt (C0RECIC/C1RECIC)
and 'message transmit successful' interrupt (C0TRMIC/ C1TRMIC).
One interrupt signals if the CAN module enters an error operating state (C01ERRIC),
i.e. 'error passive', 'bus off' and if any CAN bus error occurred in the communication
process. The CAN bus error interrupt generation can be individually disabled in the
CAN Control Register.
The wake up case will also be flagged to the CPU by an additional interrupt line
(C01WKPIC).
Interrupts
• 6 Interrupts
CAN0- Successful Transmission Interrupt
CAN0- Successful Reception Interrupt
CAN1- Successful Transmission Interrupt
CAN1- Successful Reception Interrupt
CAN0/1- Error Interrupt
- Error Passive State
- Error BusOff State
- Bus Error (this feature could be disabled separately)
CAN0/1- Wake Up Interrupt
When the CPU detects an Successful Transmission/Reception Interrupt, the CAN Status Register
must be read to determine which Mailbox has issued the interrupt.
Memory Map of the CAN0/1 Special Function Registers
This memory map is valid for both CAN channels (CAN0 and CAN1)
• CAN Mailboxes
- 16 message slots (each mailbox comprises 16 bytes (8 words))
- fixed mailbox-organization
- 'Basic CAN'-feature is composed of two regular CAN slots (#14/15) - This feature is implemented as
an option.
• CAN Mask Registers
- 3 masks for the acceptance filter (refer to section 'Mask Register and Acceptance Filter') (each mask
comprises 6 bytes)
• CAN SFR Registers
- 9 CAN Special Function Registers
Control Register
(16 Bits): controls the CAN module.
Status Register
Slot Status Register
Interrupt Control Register
Extended ID Register
Configuration Register
REC Register
TEC Register
Time Stamp Register
(16 Bits): displays the status of the CAN module.
(16 Bits): for each slot, the current content status is monitored.
(16 Bits): for each slot, the interrupts can be disabled.
(16 Bits): distinguishes between ExtendedID and StandardID
mailboxes.
(16 Bits): configuration of the bus timing
(8 Bits) : receive error counter of the CAN module
(8 Bits) : transmit error counter of the CAN module
(16 Bits): time stamp counter
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