M16C Datasheet, PDF (120/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CSelorciakl sI/yOnchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 12-2
and 12-3 list the specifications of the clock synchronous serial I/O mode. Figure 12-9 shows the UARTi
transmit/receive mode register.
Table 12-2. Specifications of clock synchronous serial I/O mode (1)
Item
Transfer data format
Transfer clock
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 01F816
= “0”) : fi/ 2(n+1) (Note 1) fi = f2SIO, f8SIO, f32SIO
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 01F816
= “1”) : Input from CLKi pin (Note 2)
Transmission/reception control
Transmission start condition
Reception start condition
• CTS function/RTS function/CTS, RTS function chosen to be invalid
• To start transmission, the following requirements must be met:
_ _{Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = “0”}
_ _{When CTS function selected, CTS input level = “L”}
• Furthermore, if external clock is selected, the following requirements must also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “0”:}
CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “1”:}
CLKi input level = “L”
• To start reception, the following requirements must be met:
_ _{Receive enable bit (bit 2 at addresses 03A516, 03AD16, 01FD16) = “1”}
_ _{Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = “1”}
_ _{Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = “0”}
• Furthermore, if external clock is selected, the following requirements must
Interrupt request
generation timing
also be met:
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “0”:}
CLKi input level = “H”
_ _{CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = “1”:}
CLKi input level = “L”
• When transmitting
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at}
address 01FD16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_ _{Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at}
address 01FD16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_ _{Interrupts requested when data transfer from UARTi receive register to}
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: Maximum 5 Mbps.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
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