M16C Datasheet, PDF (71/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(3) The NMI interrupt
•As for the NMI pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull-up) if
unused. Be sure to work on it.
•The NMI pin also serves as P8 , which is exclusively for input. Reading the contents of the P8 register
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allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when
the NMI interrupt is input.
•Do not reset the CPU with the input to the NMI pin being in the "L" state.
•Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to the
NMI pin being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down.
•Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to the
NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this
instance, the CPU is returned to the normal state by a later interrupt.
•Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
•Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0
through INT5 regardless of the CPU operation clock.
•When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 6-15 shows the procedure for changing
the INT interrupt generate factor.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
Figure 6-15. Switching condition of INT interrupt request
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