M16C Datasheet, PDF (30/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(8) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, bits 4 to 7 of the chip select control register are invalid and a
wait is applied to all external memory areas (two or three BCLK cycles). However, this is not necessary if the
oscillation frequency is less than 3MHz.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each
of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register correspond
to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK
cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0”
after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
the corresponding bits of the chip select control register must be set to “0” if using the multiplex bus to
access the external memory area.
Table 3-8 shows the software wait and bus cycles. Figure 3-8 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 3-8. Software waits and bus cycles
Area
Bus status
SFR
Internal
ROM/RAM
Separate bus
External
memory
area
Separate bus
Separate bus
Multiplex bus
Multiplex bus
Note: Always set to "0".
Wait bit
Invalid
0
1
0
0
1
0
1
Bits 4 to 7 of chip select
control register
Invalid
Invalid
Invalid
1
0
0 (Note)
0 (Note)
0 (Note)
Bus cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
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