M16C Datasheet, PDF (140/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C / 6N Group
CUAloRckT2asSypnecchiraolnMouosdeseRrieagl iIs/Oter(UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
start condition detection, and set to “0” by the stop condition detection. The acknowledgment non-
detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying
“H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the
interrupt that occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission
clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA request factor selection bits provides the
means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the special UART2 mode register (01F716) is used as the arbitration loss detection flag control bit.
Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal
data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception
buffer register (01FF16), and “1” is set in this flag when nonconformity is detected. Use the arbitration loss
detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When
setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost
detecting flag is set to "1" at the falling edge of the 9th transmission clock.
If updated the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after
completing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the special UART2 mode register is used as SCL- and L-synchronous output enabling bit. Setting
this bit to “1” resets the P71 data register to “0” in synchronization with the SCL terminal level going to “L”.
140