M16C Datasheet, PDF (148/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

S I/O3
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions for setting an SOUT3 initial value
In carrying out transmission, the output level of the SOUT3 terminal as it is before transmitting 1-bit
data can be set either to “H” or to “L”. Figure 14-4 shows the timing chart for setting an SOUT3 initial
value and how to set it.
(Example) With “H” selected for SOUT3
Signal written to the S I/O3
transmission/reception
register
SOUT3's initial value
setting bit (SM37)
S I/O3 port select bit SM33 = 0
SOUT3 initial value select bit
SM37 = 1
(SOUT3: Internal -> “H” level)
S I/O3 port select bit
(SM33)
S I/O3 port select bit
SM33 = 0 ->1
(Port select: Normal port -> SOUT3)
SOUT3 (internal)
D0
SOUT3 terminal = “H” output
SOUT3 terminal output
Port output
D0
Initial value = “H” (Note)
Signal written to the S I/O3 register
=“L” -> “H” -> “L”
(Falling edge)
Setting the SOUT3 Port selection
initial value to H (normal port -> SOUT3)
Note: The set value is output only when the external clock has been selected.
If the internal clock has been selected or if SOUT high impedance has been set,
this output goes to the high-impedance state.
SOUT3 terminal = Outputting
stored data in the S I/O3
transmission/reception register
Figure 14-4. Timing chart for setting SOUT3’s initial value and how to set it
S I/O3 operation timing
Figure 14-5 shows the S I/O3 operation timing
Transfer clock
(Note 1)
Signal written to the
S I/O3 register
S I/O3 output SOUT3
S I/O3 input SIN3
D0
D1
D2
D3
D4
D5
D6
(Note 2)
D7
Setting the S I/O3 interrupt request bit
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using
bits 0 and 1 of the S I/O3 control register. (2-division frequency, 8-division frequency, 32-division frequency)
Note 2: With the internal clock selected for the transfer clock, the SOUT3 terminal becomes to the high-impedance
state after the transfer finishes.
Figure 14-5. S I/O3 operation timing chart
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