M16C Datasheet, PDF (204/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C / 6N Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Ta = -25 °C, CM15 ="1"
unless otherwise specified)
Vcc = 5 V
Table 21-21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol
Parameter
Measuring condition
td(BCLK-AD) Address output delay time
th(BCLK-AD)
th(RD-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
th(WR-AD)
Address output hold time (WR standard)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
Chip select output delay time
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Figure 1.26.1
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
td(AD-WR)
tdZ(RD-AD)
Post-address WR signal output delay time
Address output floating start time
Note: Calculated according to the BCLK frequency as follows:
10 ⁹
th(RD – AD) =
f(BCLK) X 2
[ns]
Standard
Min. Max.
25
4
(Note)
(Note)
25
4
(Note)
(Note)
25
0
25
0
40
4
(Note)
(Note)
25
–4
(Note)
50
0
0
8
10 ⁹
th(WR – AD) =
f(BCLK) X 2
[ns]
10 ⁹
th(RD – CS) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – CS) =
f(BCLK) X 2
[ns]
td(DB – WR) =
10 ^{9 X 3}
f(BCLK) X 2 ^{– 40 [ns]}
10 ⁹
th(WR – DB) =
f(BCLK) X 2
[ns]
td(AD – ALE) =
10 ⁹
f(BCLK) X 2 ^{– 25}
[ns]
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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