M16C Datasheet, PDF (108/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timers’ functions for three-phase motor control
Sawtooth modulation
To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit
6) of three-phase PWM control register 0 (01C816). Also, set “0” in the timers A4, A1, and A2-1 control bit
(bit 1) of three-phase PWM control register 1 (01C916). In this mode, the timer registers of timers A4, A1,
and of A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer
register’s content to the counter every time the timer B2 counter’s content becomes 000016. The effective
interrupt output specification bit (bit 1) of three-phase PWM control register 0 (01C816) and the effective
interrupt output polarity selection bit (bit 0) turn nullified.
An example of U phase waveform is shown in Figure 11-8, and the description of waveform output
workings is given below. Set “1” in bit 0 (DU0) of three-phase output buffer register 0 (01CA16), and set
“0” in bit 1 (DUB0) of the same register. In addition, set “0” in bit 0 (DU1) of three-phase output buffer
register 1 (01CA16) and set “1” in bit 1 (DUB1) of the same register.
When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4
starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer
registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of
DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase buffer
register’s content is set in the three-phase shift register every time the timer B2 counter’s content be-
comes 000016.
The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when
timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one
position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U
output signal respectively. At the same time, one-shot pulses are output from the timer for setting dead
time used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L”
level of the U phase waveform, which has the opposite phase of the former. The U phase waveform
output that started from the “H” level keeps its level until the timer for setting dead time finishes outputting
one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by
the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot
pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform
changes to the “L” level. When the timer B2 counter’s content becomes 000016, the contents of the three-
phase buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents
of DUB1 and DUB0 are set in the three-phase shift register (U phase) again.
A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase
output shift register on the U phase side is used, the workings in generating a U phase waveform, which
has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In
this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of
the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of
the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2
and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase
of the former, have the corresponding timers work similarly to dealing with the U and U phases to gener-
ate an intended waveform.
Setting “1” both in bit 1 (DUB0) of three-phase buffer register 0 (01CA16) and in bit 1 (DUB1) of three-
phase buffer register 1 (01CA16) provides a means to output the U phase alone and to fix the U phase
output to “H” as shown in Figure 11-9.
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