M16C Datasheet, PDF (40/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describe the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
form the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping
the clock reduces the power consumption.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power consumption. This bit defaults to “1” when shifting to stop
mode and after a reset.
You can switch over from the main clock to the ring oscillator by changing the value of the main clock
switch bit (bit 5 at address 000C₁₆).
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset. After
oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be selected as
the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub
clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power consumption. This bit changes to “1” when shifting to
stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU and the watchdog timer, i.e. the internal clock φ, and is either
the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. After a reset the BCLK is
derived by dividing the main clock by 8 .
When shifting to stop mode, the main clock division select bit (bit 6 at 000616) is set to “1”.
(4) Peripheral function clocks
• f2, f8, f32, f2SIO2, f8SIO2, f32SIO2
The clock for the peripheral devices is derived by dividing the main clock by 2(or no division), 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
As to f2 and f2SIO2, you can select division by 2 or no division by changing the value of the peripheral
function clock select register. Select the mode without division only when Xin is 16 MHz or lower.
• f2AD
This clock is derived by dividing the main clock by 2(or no division) and is used for A-D conversion. You can
select division by 2 or no division by changing the value of the peripheral function clock select register.
• fCAN0 ,fCAN1
These clocks are derived by dividing the main clock by 1, 2, 4, 8 or 16 and they are used for the
corresponding CAN module.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It may be selected as the BCLK and for the watchdog
timer.
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