M16C Datasheet, PDF (119/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X00000002
Bit
symbol
U0IRS
Bit
name
UART0 transmit
interrupt cause select bit
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Function
(During UART mode)
RW
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
U1RRM UART1 continuous
receive mode enable bit
CLKMD0 CLK/CLKS select bit 0
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Invalid
Invalid
Invalid
Must always be “0”
RCSP Separate CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
01F716
When reset
0016
Bit
symbol
Bit
name
IICM IIC mode selection bit
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
0 : Normal mode
1 : IIC mode
Must always be “0”
RW
ABC Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
Must always be “0”
BBS Bus busy flag
LSYN SCLL sync output
enable bit
0 : STOP condition detected Must always be “0”
1 : START condition detected
0 : Disabled
1 : Enabled
Must always be “0”
(Note)
ABSCS ^{Bus collision detect}
sampling
clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
SSS
Transmit start condition
select bit
Must always be “0”
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of RxD2
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: Nothing but "0" may be written.
Figure 12-8. Serial I/O-related registers (5)
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