M16C Datasheet, PDF (215/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Outline Performance (CPU Rewrite Mode)
The CPU rewrite mode can be executed in single-chip mode, memory expansion mode and boot mode,
allowing for only the user ROM area to be rewritten.
In CPU rewrite mode, the on-chip flash memory is operated on for erase, program or read operation by
the CPU by writing a software command. Note that in this case the control program may not be located in
the internal flash memory. For example, in single-chip mode, transferred into internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to 1, transition to CPU rewrite mode
occurs and software commands can be accepted.
In CPU rewrite mode, all software commands and data are written into and read from even addresses
(address A0 of byte address = 0) 16 bits at a time. Therefore, make sure 8-bit software commands are
always written into even addresses. Data at odd addresses have no effect.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 23-1 shows the flash memory control register. Bit 0 is the RY/BY status flag, a read-only bit indicat-
ing the operating status of the flash memory. This flag is 0 (busy) during auto write and auto erase opera-
tion; otherwise, it is 1 (ready). (Its function is equivalent to that of the RY/BY pin in parallel I/O mode.) Bit
1 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to 1, so that
software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the
on-chip flash memory directly. Therefore, use the control program except in the internal flash memory to
set this bit to 0. For this bit to be set to 1, the user needs to write a 0 and then a 1 in it in succession. The
bit can be set to 0 by writing a 0 only.
Bit 2 is a lock bit disable bit. By setting this bit to 1, it is possible to disable erase and write protect (block
lock) effectuated by the lock bit data. (This function is equivalent to that of the WP pin in parallel I/O mode.)
The lock bit disable bit only disables the function of the lock bit and cannot set the lock bit itself. However,
if an erase operation is performed when this bit is 1, the lock bit data that is 0 (locked) is set to 1 (unlocked)
after erasure. For this bit to be set to 1, it is necessary to write a 0 and then a 1 in it in succession when the
CPU rewrite mode select bit is 1. This bit can be manipulated only when the CPU rewrite mode select bit
is 1.
Bit 3 is a flash memory reset bit, provided to reset the control circuit of the on-chip flash memory. This bit
is used when exiting CPU rewrite mode and when flash memory access has failed. If this bit is set to 1
when the CPU rewrite mode select bit is 1, the flash memory is reset. To deassert this reset, the bit needs
to be cleared to 0 after being set to 1.
Bit 5 is a user ROM area select bit which is effective in boot mode only. If this bit is set to 1 in boot mode,
the area to access is switched from the boot ROM area to the user ROM area. When the CPU rewrite
mode needs to be used in boot mode, set this bit to 1. Note that if the microcomputer is booted from the
user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in
boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Use
the control program outside the internal flash memory to rewrite this bit.
Figure 23-2 shows a flowchart to set and reset the CPU rewrite mode. Always be sure to follow this
flowchart.
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