M16C Datasheet, PDF (147/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

S I/O3
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 14-1. Specifications of S I/O3
Item
Transfer data format
Transfer clock
Conditions for
transmission/
reception start
Specifications
• Transfer data length: 8 bits
• With the internal clock selected (bit 6 of 01E216 = “1”): f2SIO/2(n+1),
f8SIO/2(n+1), f32SIO/2(n+1) (Note 1)
• With the external clock selected (bit 6 of 01E216): Input from the CLK3 terminal (Note 2)
• To start transmit/reception, the following requirements must be met:
- Select the synchronous clock (use bit 6 of 01E216).
Select a frequency dividing ratio if the internal clock has been selected (use bits
0 and 1 of 01E216).
- SOUT3 initial value set bit (use bit 7 of 01E216)= 1.
- S I/O3 port select bit (bit 3 of 01E216) = 1.
- Select the transfer direction (use bit 5 of 01E216)
• To use S I/O3 interrupts, the following requirements must be met:
Interrupt request
generation timing
- S I/O3 interrupt request bit (bit 3 of 004916) = 0.
• An interrupt occurs after counting eight transfer clock either in transmitting or
receiving data. (Note 3)
- In transmitting: At the time data transfer from the S I/O3 transmission/reception register finishes.
Select function
- In receiving: At the time data reception to the S I/O3 transmission/reception register finishes.
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected.
Note 1: n is a value from 0016 through FF16 set in the S I/O3 transfer rate register.
Note 2: With the external clock selected:
• To write to the S I/O3 transmission/reception register (01E216), enter the “H” level to the CLK3
terminal. Also, to write to the bit 7 (SOUT3 initial value set bit) of SI/O3 control register (01E216),
enter the “H” level to the CLK3 terminal.
• The S I/O3 circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state.
SI/O3 bit rate generator
b7
b0
Symbol
S3BRG
Address
01E316
When reset
Indeterminate
Indeterminate
Assuming that set value = n, BRG3 divides the count
source by n + 1
Values that can be set R W
0016 to FF16
SI/O3 transmit/receive register
b7
b0
Symbol
S3TRR
Address
01E016
When reset
Indeterminate
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
RW
Figure 14-3. SI/O3 related register
147