|
M16C Datasheet, PDF (127/262 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | |||
|
◁ |
Preliminary Specifications REV.B
Mitsubishi microcomputers
Specifications in this manual are tentative and subject to change.
M16C / 6N Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13-1 and 13-2 list the specifications of the UART mode. Figure 13-1 shows the
UARTi transmit/receive mode register.
Table 13-1. Specifications of UART Mode (1)
Item
Specification
Transfer data format
⢠Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
⢠Start bit: 1 bit
⢠Parity bit: Odd, even, or nothing as selected
⢠Stop bit: 1 bit or 2 bits as selected
Transfer clock
⢠When internal clock is selected (bit 3 at addresses 03A016, 03A816, 01F816=â0â) :
fi/16(n+1) (Note 1) fi = f2SIO, f8SIO, f32SIO
⢠When external clock is selected (bit 3 at addresses 03A016, 03A816, 01F816 =â1â) :
fEXT/16(n+1)(Note 1) (Note 2)
Transmission/reception control ⢠CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition ⢠To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = â1â
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = â0â
- When CTS function selected, CTS input level = âLâ
Reception start condition ⢠To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 01FD16) = â1â
- Start bit detection
Interrupt request
⢠When transmitting
generation timing
- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 01FD16) = â0â: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 01FD16) = â1â: Interrupts requested when data transmission from
UARTi transfer register is completed
⢠When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
⢠Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
⢠Framing error
This error occurs when the number of stop bits set is not detected
⢠Parity error
This error occurs when if parity is enabled, the number of 1âs in parity and
character bits does not match the number of 1âs set
⢠Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ânâ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to â1â.
127
|
▷ |