M1A3P250-VQ100 Datasheet, PDF (92/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-111 • A3P250 Global Resource
Commercial-Case Conditions: T_J = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
Input Low Delay for Global Clock
0.80 1.01 0.91 1.15 1.07 1.36 ns
t_RCKH
Input High Delay for Global Clock
0.78 1.04 0.89 1.18 1.04 1.39 ns
t_RCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
t_RCKMPWL Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
t_RCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-112 • A3P400 Global Resource
Commercial-Case Conditions: T_J = 70°C, VCC = 1.425 V
–2
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
Input Low Delay for Global Clock
0.87 1.09 0.99 1.24 1.17 1.46 ns
t_RCKH
Input High Delay for Global Clock
0.86 1.11 0.98 1.27 1.15 1.49 ns
t_RCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
t_RCKMPWL Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
t_RCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
2- 87