M1A3P250-VQ100 Datasheet, PDF (58/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-68 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL¹ IIH²
Drive
Min.
Strength V
Max.
V
Min.
V
Max. Max.
VV
Min.
V
Max. Max.
mA mA mA³ mA³ µA⁴ µA⁴
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9
11 10 10
4 mA
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17
22 10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Test Point
Datapath
35 pF
R = 1 kΩ
Test Point
Enable Path
R to VCCI for t_LZ / t_ZL / t_ZLS
R to GND for t_HZ / t_ZH / t_ZHS
35 pF for t_ZH / t_ZHS / t_ZL / t_ZLS
35 pF for t_HZ / t_LZ
Figure 2-8 • AC Loading
Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
0
Input High (V)
1.8
Measuring Point* (V)
0.9
C_LOAD (pF)
35
Note: *Measuring point = Vtrip_. See Table 2-22 on page 2-21 for a complete table of trip points.
Revision 15
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