M1A3P250-VQ100 Datasheet, PDF (84/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
CLK
Data_F
1
Data_R 6
t_DDROSUD2 t_DDROHD2
2
3
4
t_DDROREMCLR ^tDDROHD1
7
8
9
CLR
t_DDROREMCLR
t_DDROCLR2Q
Out
t_DDROCLKQ
7
2
8
3
5
10
t_DDRORECCLR
9
4
11
10
Figure 2-22 • Output DDR Timing Diagram
Timing Characteristics
Table 2-104 • Output DDR Propagation Delays
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2 –1 Std. Units
t_DDROCLKQ
Clock-to-Out of DDR for Output DDR
0.70 0.80 0.94 ns
t_DDROSUD1
Data_F Data Setup for Output DDR
0.38 0.43 0.51 ns
t_DDROSUD2
Data_R Data Setup for Output DDR
0.38 0.43 0.51 ns
t_DDROHD1
Data_F Data Hold for Output DDR
0.00 0.00 0.00 ns
t_DDROHD2
Data_R Data Hold for Output DDR
0.00 0.00 0.00 ns
t_DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
0.80 0.91 1.07 ns
t_DDROREMCLR Asynchronous Clear Removal Time for Output DDR
0.00 0.00 0.00 ns
t_DDRORECCLR Asynchronous Clear Recovery Time for Output DDR
0.22 0.25 0.30 ns
t_DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.22 0.25 0.30 ns
t_DDROCKMPWH Clock Minimum Pulse Width High for the Output DDR
0.36 0.41 0.48 ns
t_DDROCKMPWL Clock Minimum Pulse Width Low for the Output DDR
0.32 0.37 0.43 ns
F_DDOMAX
Maximum Frequency for the Output DDR
350 309 263 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
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