M1A3P250-VQ100 Datasheet, PDF (73/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Preset
Preset
Data
Enable
CLK
D
PRE
D
Q
C _DFN1E1P1
EY
E
B
A
Data Input I/O Register with:
Active High Enable
Active High Preset
Positive-Edge Triggered
CLKBUF
Core
Array
INBUF
Data_out
F
G
H
I
J
K
L
DOUT
PRE
D
Q
DFN1E1P1
E
EOUT
PRE
D
Q
DFN1E1P1
E
INBUF
Data Output Register and
Enable Output Register with:
Active High Enable
Active High Preset
Postive-Edge Triggered
Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
Revision 15
2- 68