M1A3P250-VQ100 Datasheet, PDF (87/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Timing Characteristics
Table 2-105 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
Equation
Parameter
–2
–1
Std.
Units
INV
Y = !A
t_PD
0.40
0.46
0.54
ns
AND2
Y=A·B
t_PD
0.47
0.54
0.63
ns
NAND2
Y = !(A · B)
t_PD
0.47
0.54
0.63
ns
OR2
Y=A+B
t_PD
0.49
0.55
0.65
ns
NOR2
XOR2
Y = !(A + B)
Y=A⊕B
t_PD
0.49
0.55
0.65
ns
t_PD
0.74
0.84
0.99
ns
MAJ3
XOR3
Y = MAJ(A, B, C)
t_PD
0.70
0.79
0.93
ns
Y=A⊕B⊕C
t_PD
0.87
1.00
1.17
ns
MUX2
Y = A !S + B S
t_PD
0.51
0.58
0.68
ns
AND3
Y=A·B·C
t_PD
0.56
0.64
0.75
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a
representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E
Macro Library Guide.
Data
D
Out
Q
DFN1
CLK
Data
D
Out
Q
En _DFN1E1
CLK
Data
D
Q ^Out
DFN1C1
CLK
CLR
Figure 2-25 • Sample of Sequential Cells
PRE
Data
D
Out
Q
En _DFI1E1P1
CLK
Revision 15
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