M1A3P250-VQ100 Datasheet, PDF (31/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-29 • I/O Output Buffer Maximum Resistances ¹
Applicable to Standard Plus I/O Banks
Standard
Drive Strength
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
R_PULL-DOWN (Ω)²
100
R_PULL-UP (Ω)³
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
3.3 V LVCMOS Wide Range⁴
16 mA
100 µA
25
75
Same as regular Same as regular
3.3 V LVCMOS 3.3 V LVCMOS
2.5 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
3.3 V PCI/PCI-X
Per PCI/PCI-X
25
75
specification
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located at
http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R_{(PULL-DOWN-MAX)} = (VOLspec) / IOLspec
3. R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / IOHspec
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B
specification.
Revision 15
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