M1A3P250-VQ100 Datasheet, PDF (13/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹
Applicable to Advanced I/O Banks
Single-Ended
C_LOAD (pF)
VCCI (V)
Static Power
PDC3 (mW)²
Dynamic Power
PAC10 (µW/MHz)³
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
3.3 V LVCMOS Wide Range⁴
35
3.3
–
468.67
–
468.67
2.5 V LVCMOS
35
2.5
–
267.48
1.8 V LVCMOS
35
1.8
–
149.46
1.5 V LVCMOS
(JESD8-11)
35
1.5
–
103.12
3.3 V PCI
10
3.3
–
201.02
3.3 V PCI-X
10
3.3
–
201.02
Differential
LVDS
–
2.5
7.74
88.92
LVPECL
–
3.3
19.54
166.52
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings¹
Applicable to Standard Plus I/O Banks
Single-Ended
C_LOAD (pF)
VCCI (V)
Static Power
PDC3 (mW)²
Dynamic Power
PAC10 (µW/MHz)³
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
3.3 V LVCMOS Wide Range⁴
35
3.3
2.5 V LVCMOS
35
2.5
1.8 V LVCMOS
35
1.8
1.5 V LVCMOS (JESD8-11)
35
1.5
3.3 V PCI
10
3.3
–
452.67
–
452.67
–
258.32
–
133.59
–
92.84
–
184.92
3.3 V PCI-X
10
3.3
–
184.92
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P_DC3 is the static power (where applicable) measured on VMV.
3. P_AC10 is the total dynamic power measured on VCC and VMV.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 15
2-8