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M1A3P250-VQ100 Datasheet, PDF (62/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
ProASIC3 Flash Family FPGAs
Table 2-73 • 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Strength
2 mA
Speed
Grade
Std.
tDOUT tDP
0.66 14.80
tDIN
0.04
tPY
1.20
tEOUT tZL
tZH
tLZ
0.43 13.49 14.80 2.25
tHZ tZLS tZHS Units
1.46 15.73 17.04 ns
–1
0.56 12.59 0.04 1.02 0.36 11.48 12.59 1.91 1.25 13.38 14.49 ns
–2
0.49 11.05 0.03 0.90 0.32 10.08 11.05 1.68 1.09 11.75 12.72 ns
4 mA
Std. 0.66 9.90 0.04 1.20 0.43 9.73 9.90 2.65 2.50 11.97 12.13 ns
–1
0.56 8.42 0.04 1.02 0.36 8.28 8.42 2.26 2.12 10.18 10.32 ns
–2
0.49 7.39 0.03 0.90 0.32 7.27 7.39 1.98 1.86 8.94 9.06 ns
6 mA
Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns
–1
0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns
–2
0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns
8 mA
Std. 0.66 7.44 0.04 1.20 0.43 7.58 7.32 2.94 2.99 9.81 9.56 ns
–1
0.56 6.33 0.04 1.02 0.36 6.44 6.23 2.50 2.54 8.35 8.13 ns
–2
0.49 5.55 0.03 0.90 0.32 5.66 5.47 2.19 2.23 7.33 7.14 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-74 • 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Applicable to Standard I/O Banks
Drive
Strength
2 mA
Speed
Grade
Std.
tDOUT
0.66
tDP
11.21
tDIN
0.04
tPY
1.20
tEOUT
0.43
tZL
8.53
tZH
11.21
tLZ
1.99
tHZ
1.21
Units
ns
–1
0.56 9.54 0.04 1.02 0.36 7.26 9.54 1.69 1.03
ns
–2
0.49 8.37 0.03 0.90 0.32 6.37 8.37 1.49 0.90
ns
4 mA
Std.
0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48
ns
–1
0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11
ns
–2
0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
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