M1A3P250-VQ100 Datasheet, PDF (200/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Datasheet Information
Revision
Changes
Revision 9 (Oct 2009)
Product Brief v1.3
The CS121 package was added to table under "Features and Benefits" section,
the "I/Os Per Package ¹" table, Table 1 • ProASIC3 FPGAs Package Sizes
Dimensions, "ProASIC3 Ordering Information", and the "Temperature Grade
Offerings" table.
"ProASIC3 Ordering Information" was revised to include the fact that some RoHS
compliant packages are halogen-free.
Packaging v1.5
The "CS121 – Bottom View" figure and pin table for A3P060 are new.
Revision 8 (Aug 2009) All references to M7 devices (CoreMP7) and speed grade –F were removed from
Product Brief v1.2
this document.
Table 1-1 I/O Standards supported is new.
The I/Os with Advanced I/O Standards section was revised to add definitions of
hot-swap and cold-sparing.
DC and Switching
Characteristics v1.4
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
I_IL and I_IH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables.
–F was removed from the datasheet. The speed grade is no longer supported.
The notes in Table 2-2 • Recommended Operating Conditions ¹ were updated.
Table 2-4 • Overshoot and Undershoot Limits ¹ was updated.
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
In Table 2-116 • RAM4K9, the following specifications were removed:
t_WRO
t_CCKH
In Table 2-117 • RAM512X18, the following specifications were removed:
t_WRO
t_CCKH
In the title of Table 2-74 • 1.8 V LVCMOS High Slew, VCCI had a typo. It was
changed from 3.0 V to 1.7 V.
Revision 7 (Feb 2009) The "Advanced I/O" section was revised to add a bullet regarding wide range
Product Brief v1.1
power supply voltage support.
The table under "Features and Benefits" section, was updated to include a value
for typical equivalent macrocells for A3P250.
The QN48 package was added to the following tables: the table under "Features
and Benefits" section, "I/Os Per Package ¹" "ProASIC3 FPGAs Package Sizes
Dimensions", and "Temperature Grade Offerings".
The number of singled-ended I/Os for QN68 was added to the "I/Os Per
Package ¹" table.
The Wide Range I/O Support section is new.
Revision 6 (Dec 2008) The "QN48 – Bottom View" section is new.
Packaging v1.4
The "QN68" pin table for A3P030 is new.
Page
I – IV
III
4-15
N/A
1-7
1-7
N/A
N/A
N/A
2-2
2-2
2-6
2-94
2-96
2-57
I
I
N/A
1-7
4-1
4-5
5-4
Revision 15