M1A3P250-VQ100 Datasheet, PDF (83/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Output DDR Module
ProASIC3 Flash Family FPGAs
Output DDR
Data_F
(from core)
A
X
FF1
B
CLK
X
CLKBUF
C
X
Data_R
(from core)
D
X
FF2
CLR
BX
INBUF
CX
Out
0
E
X
1
OUTBUF
DDR_OUT
Figure 2-21 • Output DDR Timing Model
Table 2-103 • Parameter Definitions
Parameter Name
Parameter Definition
t_DDROCLKQ
t_DDROCLR2Q
t_DDROREMCLR
t_DDRORECCLR
t_DDROSUD1
t_DDROSUD2
t_DDROHD1
t_DDROHD2
Clock-to-Out
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
Measuring Nodes (from, to)
B, E
C, E
C, B
C, B
A, B
D, B
A, B
D, B
Revision 15
2- 78