M1A3P250-VQ100 Datasheet, PDF (16/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices
Definition
Device Specific Static Power (mW)
Parameter
PDC1
Array static power in Active mode
See Table 2-7 on page 2-6.
PDC2
I/O input pin static power (standard-dependent)
See Table 2-8 on page 2-6 through
Table 2-10 on page 2-7.
PDC3
I/O output pin static power (standard-dependent)
See Table 2-11 on page 2-8 through
Table 2-13 on page 2-9.
PDC4
Static PLL contribution
2.55 mW
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-7 on page 2-6.
Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power
spreadsheet calculator or SmartPower tool in Libero SoC software.
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
• The number of PLLs as well as the number and the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on
page 2-13.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on
page 2-13.
• Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-17 on page 2-13. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P_TOTAL
P_TOTAL = P_STAT + P_DYN
P_STAT is the total static power consumption.
P_DYN is the total dynamic power consumption.
Total Static Power Consumption—P_STAT
P_STAT = P_DC1 + N_INPUTS* P_DC2 + N_OUTPUTS* P_DC3
N_INPUTS is the number of I/O input buffers used in the design.
N_OUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption—P_DYN
P_DYN = P_CLOCK + P_S-CELL + P_C-CELL + P_NET + P_INPUTS + P_OUTPUTS + P_MEMORY + P_PLL
Global Clock Contribution—P_CLOCK
P_CLOCK = (P_AC1 + N_SPINE*P_AC2 + N_ROW*P_AC3 + N_S-CELL* P_AC4) * F_CLK
N_SPINE is the number of global spines used in the user design—guidelines are provided in the "Spine
Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide.
Revision 15
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