M1A3P250-VQ100 Datasheet, PDF (207/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Revision
Advance v0.3
Advance v0.2
ProASIC3 Flash Family FPGAs
Changes
Page
The "PLL Macro" section was updated. EXTFB information was removed from 2-15
this section.
The CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT} was updated in Table 2-
11 • ProASIC3 CCC/PLL Specification
2-29
EXTFB was removed from Figure 2-27 • CCC/PLL Macro.
2-28
Table 2-13 • ProASIC3 I/O Features was updated.
2-30
The "Hot-Swap Support" section was updated.
2-33
The "Cold-Sparing Support" section was updated.
2-34
"Electrostatic Discharge (ESD) Protection" section was updated.
2-35
The LVPECL specification in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance 2-64
Capabilities in ProASIC3 Devices was updated.
In the Bank 1 area of Figure 2-72, VMV2 was changed to VMV1 and VCCIB2 was
changed to VCC_IB1.
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
2-97
2-50
The "JTAG Pins" section was updated.
2-51
"128-Bit AES Decryption" section was updated to include M7 device information. 2-53
Table 3-6 was updated.
3-6
Table 3-7 was updated.
3-6
In Table 3-11, PAC4 was updated.
3-93-8
Table 3-20 was updated.
3-20
The note in Table 3-32 was updated.
3-27
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-31 to 3-
73
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-85 to
3-90
F_TCKMAX was updated in Table 3-110.
Figure 2-11 was updated.
3-97
2-9
The "Clock Resources (VersaNets)" section was updated.
2-9
The "VersaNet Global Networks and Spine Access" section was updated.
2-9
The "PLL Macro" section was updated.
2-15
Figure 2-27 was updated.
2-28
Figure 2-20 was updated.
2-19
Table 2-5 was updated.
2-25
Table 2-6 was updated.
2-25
The "FIFO Flag Usage Considerations" section was updated.
2-27
Table 2-13 was updated.
2-30
Figure 2-24 was updated.
2-31
The "Cold-Sparing Support" section is new.
2-34
Revision 15
5- 11