M1A3P250-VQ100 Datasheet, PDF (112/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-14 for more details.
Timing Characteristics
Table 2-125 • JTAG 1532
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
t_DISU
Test Data Input Setup Time
0.50 0.57 0.67
ns
t_DIHD
Test Data Input Hold Time
1.00 1.13 1.33
ns
t_TMSSU
Test Mode Select Setup Time
0.50 0.57 0.67
ns
t_TMDHD
Test Mode Select Hold Time
1.00 1.13 1.33
ns
t_TCK2Q
Clock to Q (data out)
6.00 6.80 8.00
ns
t_RSTB2Q
Reset to Q (data out)
20.00 22.67 26.67 ns
F_TCKMAX
TCK Maximum Frequency
25.00 22.00 19.00 MHz
t_TRSTREM
ResetB Removal Time
0.00 0.00 0.00
ns
t_TRSTREC
ResetB Recovery Time
0.20 0.23 0.27
ns
t_TRSTMPW
ResetB Minimum Pulse
TBD TBD TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for
derating values.
Revision 15
2- 107