M1A3P250-VQ100 Datasheet, PDF (48/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial-Case Conditions: T_J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Strength
100 µA
Equiv.
Software
Default
Drive
Strength
Option¹
2 mA
Speed
Grade
Std.
t_DOUT t_DP t_DIN t_PY t_EOUT t_ZL t_ZH t_LZ t_HZ t_ZLS t_ZHS Units
0.60 14.97 0.04 1.52 0.43 14.97 12.79 3.52 3.41 18.36 16.18 ns
–1 0.51 12.73 0.04 1.29 0.36 12.73 10.88 2.99 2.90 15.62 13.77 ns
–2 0.45 11.18 0.03 1.14 0.32 11.18 9.55 2.63 2.55 13.71 12.08 ns
100 µA
4 mA
Std. 0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns
–1 0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns
–2 0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21 ns
100 µA
6 mA
Std. 0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns
–1 0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns
–2 0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21 ns
100 µA
8 mA
Std. 0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns
–1 0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71 ns
–2 0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65 ns
100 µA
16 mA
Std. 0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns
–1 0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71 ns
–2 0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65 ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 15
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