M1A3P250-VQ100 Datasheet, PDF (201/210 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

ProASIC3 Flash Family FPGAs
Revision
Changes
Page
Revision 5 (Aug 2008) TJ, Maximum Junction Temperature, was changed to 100° from 110º in the 2-5
DC and Switching
"Thermal Characteristics" section and EQ 1. The calculated result of Maximum
Characteristics v1.3 ^{Power Allowed has thus changed to 1.463 W from 1.951 W.}
Values for the A3P015 device were added to Table 2-7 • Quiescent Supply 2-6
Current Characteristics.
Values for the A3P015 device were added to Table 2-14 • Different Components 2-10, 2-11
Contributing to Dynamic Power Consumption in ProASIC3 Devices. P_AC14 was
removed. Table 2-15 • Different Components Contributing to the Static Power
Consumption in ProASIC3 Devices is new.
The "PLL Contribution—PPLL" section was updated to change the P_PLL formula
from P_AC13 + P_AC14 * F_CLKOUT to P_DC4 + P_AC13 * F_CLKOUT.
Both fall and rise values were included for t_DDRISUD and t_DDRIHD in Table 2-102 •
Input DDR Propagation Delays.
2-13
2-77
Table 2-107 • A3P015 Global Resource is new.
2-85
The typical value for Delay Increments in Programmable Delay Blocks was 2-89
changed from 160 to 200 in Table 2-115 • ProASIC3 CCC/PLL Specification.
Revision 4 (Jun 2008) Table note references were added to Table 2-2 • Recommended Operating 2-2
DC and Switching
Conditions ¹, and the order of the table notes was changed.
Characteristics v1.2
The title for Table 2-4 • Overshoot and Undershoot Limits ¹ was modified to 2-2
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os."
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
Table 2-29 • I/O Output Buffer Maximum Resistances ¹ was revised to include
values for 3.3 V PCI/PCI-X.
2-6
2-26
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels was 2-65
updated.
Revision 3 (Jun 2008) Pin numbers were added to the "QN68 – Bottom View" package diagram. Note 2 4-3
Packaging v1.3
was added below the diagram.
The "QN132 – Bottom View" package diagram was updated to include D1 to D4. 4-6
In addition, note 1 was changed from top view to bottom view, and note 2 is new.
Revision 2 (Feb 2008) This document was divided into two sections and given a version number, starting N/A
Product Brief v1.0
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
This document was updated to include A3P015 device information. QN68 is a N/A
new package that was added because it is offered in the A3P015. The following
sections were updated:
"Features and Benefits"
"ProASIC3 Ordering Information"
"Temperature Grade Offerings"
"ProASIC3 Flash Family FPGAs"
"A3P015 and A3P030" note
Introduction and Overview (NA)
Revision 15
5-5