PIC18F1XK22 Datasheet, PDF (99/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
FIGURE 9-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
T0CKI pin
T0SE
0
Sync with
1
Internal
Programmable ₁
Prescaler
Clocks
(2 TCY Delay)
T0CS
3
T0PS<2:0>
PSA
TMR0L
8
TMR0
High Byte
8
Set
TMR0IF
on Overflow
8
TMR0H
Read TMR0L
Write TMR0L
8
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
8
Internal Data Bus
9.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON register which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
9.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
9.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clear-
ing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
INTCON
PORTA
TMR0H
TMR0L
TRISA
T0CON
Legend:
GIE/GIEH PEIE/GIEL TMR0IE
RA7
RA6
RA5
Timer0 Register, High Byte
Timer0 Register, Low Byte
—
—
TRISA5
TMR0ON T08BIT T0CS
Shaded cells are not used by Timer0.
INT0IE
RA4
TRISA4
T0SE
RABIE
RA3
—
PSA
Bit 2
Bit 1
TMR0IF INT0IF
RA2
RA1
TRISA2 TRISA1
T0PS2 T0PS1
Bit 0
RABIF
RA0
TRISA0
T0PS0
Reset
Values
on page
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 2010 Microchip Technology Inc.
Preliminary
DS41365D-page 99