PIC18F1XK22 Datasheet, PDF (240/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
TABLE 19-1: SRCLK FREQUENCY TABLE
SRCLK
Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz
111
512
110
256
101
128
100
64
011
32
010
16
001
8
000
4
25.6 s
12.8 s
6.4 s
3.2 s
1.6 s
0.8 s
0.4 s
0.2 s
32 s
16 s
8 s
4 s
2 s
1 s
0.5 s
0.25 s
64 s
32 s
16 s
8 s
4 s
2 s
1 s
0.5 s
128 s
64 s
32 s
16 s
8 s
4 s
2 s
1 s
FOSC = 1 MHz
512 s
256 s
128 s
64 s
32 s
16 s
8 s
4 s
REGISTER 19-1: SRCON0: SR LATCH CONTROL REGISTER
R/W-0
SRLEN
bit 7
R/W-0
SRCLK2
R/W-0
SRCLK1
R/W-0
SRCLK0
R/W-0
SRQEN
R/W-0
SRNQEN
R/W-0
SRPS
R/W-0
SRPR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented
‘0’ = Bit is cleared
C = Clearable only bit
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
SRLEN: SR Latch Enable bit⁽¹⁾
1 = SR latch is enabled
0 = SR latch is disabled
SRCLK<2:0>⁽¹⁾: SR Latch Clock divider bits
000 = 1/4 Peripheral cycle clock
001 = 1/8 Peripheral cycle clock
010 = 1/16 Peripheral cycle clock
011 = 1/32 Peripheral cycle clock
100 = 1/64 Peripheral cycle clock
101 = 1/128 Peripheral cycle clock
110 = 1/256 Peripheral cycle clock
111 = 1/512 Peripheral cycle clock
SRQEN: SR Latch Q Output Enable bit
1 = Q is present on the RA2 pin
0 = Q is internal only
SRNQEN: SR Latch Q Output Enable bit
1 = Q is present on the RC4 pin
0 = Q is internal only
SRPS: Pulse Set Input of the SR Latch bit
1 = Pulse input
0 = Always reads back ‘0’
SRPR: Pulse Reset Input of the SR Latch bit
1 = Pulse input
0 = Always reads back ‘0’
Changing the SRCLK bits while the SR latch is enabled may cause false triggers to the set and Reset
inputs of the latch.
DS41365D-page 240
Preliminary
 2010 Microchip Technology Inc.