PIC18F1XK22 Datasheet, PDF (148/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
14.3.2 OPERATION
The MSSP module functions are enabled by setting
SSPEN bit of the SSPCON1 register.
The SSPCON1 register allows control of the I²C
operation. Four mode selection bits of the SSPCON1
register allow one of the following I²C modes to be
selected:
• I²C Master mode, clock = (FOSC/(4*(SSPADD + 1))
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I²C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I²C Firmware Controlled Master mode, slave is
Idle
Selection of any I²C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRIS bits
Note:
To ensure proper operation of the module,
pull-up resistors must be provided exter-
nally to the SCL and SDA pins.
14.3.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required
(slave-transmitter).
The I²C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware
automatically will generate the Acknowledge (ACK)
pulse and load the SSPBUF register with the received
value currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF bit of the SSPSTAT regis-
ter, is set before the transfer is received.
• The overflow bit, SSPOV bit of the SSPCON1
register, is set before the transfer is received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. The BF bit is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I²C specification, as well as the requirement of the
MSSP module, are shown in Section 25.0 “Electrical
Specifications”.
14.3.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF of the PIR1 reg-
ister, is set (interrupt is generated, if enabled) on
the falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W of the SSPSTAT register must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA of the SSPSTAT register are set).
2. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
3. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set). If the address
matches then the SCL is held until the next step.
Otherwise the SCL line is not held.
5. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
6. Update the SSPADD register with the first (high)
byte of address. (This will clear bit UA and
release a held SCL line.)
7. Receive Repeated Start condition.
8. Receive first (high) byte of address with R/W bit
set (bits SSPIF, BF, R/W are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
10. Load SSPBUF with byte the slave is to transmit,
sets the BF bit.
11. Set the CKP bit to release SCL.
DS41365D-page 148
Preliminary
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