PIC18F1XK22 Datasheet, PDF (382/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
Interrupt..................................................................... 108
Operation .................................................................. 107
Output ....................................................................... 108
Timer3 ............................................................................... 109
16-Bit Read/Write Mode............................................ 112
Associated Registers ................................................ 112
Operation .................................................................. 110
Oscillator ........................................................... 109, 112
Overflow Interrupt ............................................. 109, 112
Special Event Trigger (CCP)..................................... 112
TMR3H Register ....................................................... 109
TMR3L Register ........................................................ 109
Timing Diagrams
A/D Conversion ......................................................... 357
Acknowledge Sequence ........................................... 170
Asynchronous Reception .......................................... 186
Asynchronous Transmission ..................................... 182
Asynchronous Transmission (Back to Back) ............ 183
Auto Wake-up Bit (WUE) During Normal Operation . 197
Auto Wake-up Bit (WUE) During Sleep .................... 197
Automatic Baud Rate Calculator ............................... 195
Baud Rate Generator with Clock Arbitration ............. 164
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 173
Brown-out Reset (BOR) ............................................ 353
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................ 174
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................ 175
Bus Collision During a Start Condition (SCL = 0) ..... 173
Bus Collision During a Stop Condition (Case 1) ....... 176
Bus Collision During a Stop Condition (Case 2) ....... 176
Bus Collision During Start Condition (SDA only) ...... 172
Bus Collision for Transmit and Acknowledge............ 171
CLKOUT and I/O....................................................... 352
Clock Synchronization .............................................. 157
Clock Timing ............................................................. 349
Clock/Instruction Cycle ............................................... 31
Comparator Output ................................................... 221
Enhanced Capture/Compare/PWM (ECCP) ............. 356
Fail-Safe Clock Monitor (FSCM) ................................. 26
First Start Bit Timing ................................................. 165
Full-Bridge PWM Output ........................................... 122
Half-Bridge PWM Output .................................. 120, 128
I²C Bus Data ............................................................. 363
I²C Bus Start/Stop Bits.............................................. 362
I²C Master Mode (7 or 10-Bit Transmission) ............ 168
I²C Master Mode (7-Bit Reception) ........................... 169
I²C Slave Mode (10-Bit Reception, SEN = 0) ........... 152
I²C Slave Mode (10-Bit Reception, SEN = 1) ........... 159
I²C Slave Mode (10-Bit Transmission)...................... 153
I²C Slave Mode (7-bit Reception, SEN = 0).............. 150
I²C Slave Mode (7-Bit Reception, SEN = 1) ............. 158
I²C Slave Mode (7-Bit Transmission)........................ 151
I²C Slave Mode General Call Address Sequence
(7 or 10-Bit Address Mode).............................. 160
I²C Stop Condition Receive or Transmit Mode ......... 170
Internal Oscillator Switch Timing................................. 23
PWM Auto-shutdown
Auto-restart Enabled ......................................... 127
Firmware Restart .............................................. 126
PWM Direction Change ............................................ 123
PWM Direction Change at Near 100% Duty Cycle ... 124
PWM Output (Active-High)........................................ 118
PWM Output (Active-Low) ........................................ 119
Repeat Start Condition ............................................. 166
Reset, WDT, OST and Power-up Timer ................... 353
Send Break Character Sequence ............................. 198
Slave Synchronization .............................................. 141
Slow Rise Time (MCLR Tied to VDD, VDD Rise >
TPWRT).............................................................. 255
SPI Master Mode (CKE = 1, SMP = 1) ..................... 360
SPI Mode (Master Mode).......................................... 140
SPI Mode (Slave Mode, CKE = 0) ............................ 142
SPI Mode (Slave Mode, CKE = 1) ............................ 142
SPI Slave Mode (CKE = 0) ....................................... 361
SPI Slave Mode (CKE = 1) ....................................... 361
Synchronous Reception (Master Mode, SREN) ....... 202
Synchronous Transmission ...................................... 200
Synchronous Transmission (Through TXEN) ........... 200
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD) ......................................... 255
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 1) .................................. 254
Time-out Sequence on Power-up (MCLR
Not Tied to VDD, Case 2) .................................. 254
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise < TPWRT) ...................... 254
Timer0 and Timer1 External Clock ........................... 355
Transition for Entry to Sleep Mode ........................... 235
Transition for Wake from Sleep (HSPLL) ................. 235
Transition Timing for Entry to Idle Mode................... 236
Transition Timing for Wake from Idle to Run Mode .. 236
USART Synchronous Receive (Master/Slave) ......... 359
USART Synchronous Transmission
(Master/Slave) .................................................. 359
Timing Diagrams and Specifications
A/D Conversion Requirements ................................. 357
PLL Clock ................................................................. 351
Timing Parameter Symbology .......................................... 348
Timing Requirements
I²C Bus Data............................................................. 364
I2C Bus Start/Stop Bits ............................................. 363
SPI Mode .................................................................. 362
Top-of-Stack Access........................................................... 28
TRISA Register................................................................... 81
TRISB Register............................................................. 86, 90
TSTFSZ ............................................................................ 317
Two-Speed Start-up.......................................................... 261
Two-Word Instructions
Example Cases........................................................... 32
TXREG ............................................................................. 181
TXSTA Register................................................................ 188
BRGH Bit .................................................................. 191
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 359
Requirements, Synchronous Transmission...... 359
Timing Diagram, Synchronous Receive ........... 359
Timing Diagram, Synchronous Transmission... 359
V
Voltage Reference (VR)
Specifications ........................................................... 358
Voltage Reference. See Comparator Voltage Reference
(CVREF)
Voltage References
Fixed Voltage Reference (FVR)................................ 244
VR Stabilization ........................................................ 244
DS41365D-page 382
Preliminary
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