PIC18F1XK22 Datasheet, PDF (381/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
VREFCON2 .............................................................. 246
WDTCON (Watchdog Timer Control) ....................... 272
WPUA (Weak Pull-up PORTA) ................................... 82
WPUB (Weak Pull-up PORTB) ................................... 87
RESET .............................................................................. 307
Reset State of Registers ................................................... 256
Resets ....................................................................... 249, 261
Brown-out Reset (BOR) ............................................ 261
Oscillator Start-up Timer (OST) ................................ 261
Power-on Reset (POR) ............................................. 261
Power-up Timer (PWRT) .......................................... 261
RETFIE ............................................................................. 308
RETLW ............................................................................. 308
RETURN ........................................................................... 309
Return Address Stack ......................................................... 28
Return Stack Pointer (STKPTR) ......................................... 29
Revision History ................................................................ 373
RLCF................................................................................. 309
RLNCF .............................................................................. 310
RRCF ................................................................................ 310
RRNCF ............................................................................. 311
S
SCK................................................................................... 135
SDI .................................................................................... 135
SDO .................................................................................. 135
SEC_IDLE Mode............................................................... 236
SEC_RUN Mode ............................................................... 234
Serial Clock, SCK ............................................................. 135
Serial Data In (SDI) ........................................................... 135
Serial Data Out (SDO) ...................................................... 135
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................. 311
Shoot-through Current ...................................................... 128
Single-Supply ICSP Programming.
Slave Select (SS) .............................................................. 135
Slave Select Synchronization ........................................... 141
SLEEP .............................................................................. 312
Sleep Mode ....................................................................... 235
SLRCON Register............................................................... 96
Software Simulator (MPLAB SIM)..................................... 329
SPBRG ............................................................................. 191
SPBRGH ........................................................................... 191
Special Event Trigger........................................................ 211
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ............................................ 261
Special Function Registers ................................................. 37
Map ............................................................................. 38
SPI Mode
Typical Master/Slave Connection ............................. 139
SPI Mode (MSSP)
Associated Registers ................................................ 143
Bus Mode Compatibility ............................................ 143
Effects of a Reset...................................................... 143
Enabling SPI I/O ....................................................... 139
Master Mode ............................................................. 140
Operation .................................................................. 138
Operation in Power Managed Modes ....................... 143
Serial Clock............................................................... 135
Serial Data In ............................................................ 135
Serial Data Out ......................................................... 135
Slave Mode ............................................................... 141
Slave Select .............................................................. 135
Slave Select Synchronization ................................... 141
SPI Clock .................................................................. 140
Typical Connection ................................................... 139
SR Latch ........................................................................... 239
Associated Registers................................................ 241
SRCON0 Register ............................................................ 240
SRCON1 Register ............................................................ 241
SS ..................................................................................... 135
SSP
Typical SPI Master/Slave Connection ...................... 139
SSPADD Register............................................................. 155
SSPCON1 Register .................................................. 137, 146
SSPCON2 Register .......................................................... 147
SSPMSK Register ............................................................ 154
SSPOV ............................................................................. 167
SSPOV Status Flag .......................................................... 167
SSPSTAT Register ................................................... 136, 145
R/W Bit ............................................................. 148, 149
Stack Full/Underflow Resets............................................... 30
Standard Instructions........................................................ 277
STATUS Register ............................................................... 42
STKPTR Register ............................................................... 29
SUBFSR ........................................................................... 323
SUBFWB .......................................................................... 312
SUBLW ............................................................................. 313
SUBULNK......................................................................... 323
SUBWF............................................................................. 313
SUBWFB .......................................................................... 314
SWAPF ............................................................................. 314
T
T0CON Register ................................................................. 97
T1CON Register ............................................................... 101
T2CON Register ............................................................... 107
T3CON Register ............................................................... 109
Table Pointer Operations (table)......................................... 52
Table Reads/Table Writes .................................................. 30
TBLRD .............................................................................. 315
TBLWT ............................................................................. 316
Thermal Considerations.................................................... 347
Time-out in Various Situations (table)............................... 253
Timer0 ................................................................................ 97
Associated Registers.................................................. 99
Operation.................................................................... 98
Overflow Interrupt ....................................................... 99
Prescaler .................................................................... 99
Prescaler Assignment (PSA Bit)................................. 99
Prescaler Select (T0PS2:T0PS0 Bits) ........................ 99
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode............................... 98
Source Edge Select (T0SE Bit) .................................. 98
Source Select (T0CS Bit) ........................................... 98
Specifications ........................................................... 355
Switching Prescaler Assignment ................................ 99
Timer1 .............................................................................. 101
16-Bit Read/Write Mode ........................................... 104
Associated Registers................................................ 106
Interrupt .................................................................... 105
Modes of Operation .................................................. 104
Operation.................................................................. 102
Oscillator........................................................... 101, 104
Overflow Interrupt ..................................................... 101
Resetting, Using the CCP Special Event Trigger ..... 105
Specifications ........................................................... 355
TMR1H Register....................................................... 101
TMR1L Register ....................................................... 101
Use as a Real-Time Clock ........................................ 105
Timer2 .............................................................................. 107
Associated Registers................................................ 108
 2010 Microchip Technology Inc.
Preliminary
DS41365D-page 381