PIC18F1XK22 Datasheet, PDF (41/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
TABLE 3-2: REGISTER FILE SUMMARY (PIC18F1XK22/LF1XK22) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
page:
SPBRGH
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISC
TRISB
TRISA
LATC
LATB
LATA
PORTC
PORTB
PORTA
ANSELH
ANSEL
IOCB
IOCA
WPUB
WPUA
SLRCON
SSPMSK
CM1CON0
CM2CON1
CM2CON0
SRCON1
SRCON0
Legend:
Note 1:
2:
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
EUSART Receive Register
EUSART Transmit Register
CSRC
TX9
TXEN
SYNC
SPEN
RX9
SREN
CREN
EEADR7 EEADR6 EEADR5 EEADR4
SENDB
ADDEN
EEADR3
BRGH
FERR
EEADR2
TRMT
OERR
EEADR1
TX9D
RX9D
EEADR0
0000 0000 259, 191
0000 0000 259, 191
0000 0000 259, 189
0000 0000 259, 188
0000 0010 259, 188
0000 000x 259, 189
0000 0000 259, 49,
59
EEPROM Data Register
0000 0000 259, 49,
59
EEPROM Control Register 2 (not a physical register)
0000 0000 259, 49,
59
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 259, 49,
59
OSCFIP
C1IP
C2IP
EEIP
BCLIP
—
TMR3IP
—
1111 111- 260, 75
OSCFIF
C1IF
C2IF
EEIF
BCLIF
—
TMR3IF
—
0000 000- 260, 71
OSCFIE
C1IE
C2IE
EEIE
BCLIE
—
TMR3IE
—
0000 000- 260, 73
—
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP ^{-111 1111 260, 74}
—
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF ^{-000 0000 260, 70}
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE ^{-000 0000 260, 72}
INTSRC
TRISC7
PLLEN
TRISC6
TUN5
TRISC5
TUN4
TRISC4
TUN3
TRISC3
TUN2
TRISC2
TUN1
TRISC1
TUN0
TRISC0
0000 0000 22, 260
1111 1111 260, 90
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ---- 260, 86
—
—
TRISA5
TRISA4
—
TRISA2
TRISA1
TRISA0 ^{--11 -111 260, 81}
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0 ^{xxxx xxxx 260, 91}
LATB7
LATB6
LATB5
LATB4
—
—
—
—
xxxx ---- 260, 87
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0 ^{--xx -xxx 260, 82}
RC7
RB7
RC6
RB6
RC5
RB5
RC4
RB4
RC3
—
RC2
—
RC1
—
RC0
—
xxxx xxxx 260, 90
xxxx ---- 260, 86
—
—
RA5
RA4
RA3⁽²⁾
RA2
RA1
RA0 ^{--xx xxxx 260, 81}
—
ANS7
IOCB7
—
WPUB7
—
—
ANS6
IOCB6
—
WPUB6
—
—
ANS5
IOCB5
IOCA5
WPUB5
WPUA5
—
ANS4
IOCB4
IOCA4
WPUB4
WPUA4
ANS11
ANS3
—
IOCA3
—
WPUA3
ANS10
ANS2
—
IOCA2
—
WPUA2
ANS9
ANS1
—
IOCA1
—
WPUA1
ANS8
ANS0
—
IOCA0
—
WPUA0
---- 1111 260, 95
1111 1111 260, 94
0000 ---- 260, 87
--00 0000 260, 82
1111 ---- 260, 87
--11 1111 257, 82
—
MSK7
C1ON
—
MSK6
C1OUT
—
MSK5
C1OE
—
MSK4
C1POL
—
MSK3
C1SP
SLRC
MSK2
C1R
SLRB
MSK1
C1CH1
SLRA
MSK0
C1CH0
---- -111 260, 96
1111 1111 260, 154
0000 1000 260, 227
MC1OUT MC2OUT C1RSEL C2RSEL
C1HYS
C2HYS
C1SYNC C2SYNC 0000 0000 260, 228
C2ON
C2OUT
C2OE
C2POL
C2SP
C2R
C2CH1
C2CH0 0000 1000 260, 228
SRSPE SRSCKE SRSC2E SRSC1E
SRRPE
SRRCKE
SRRC2E SRRC1E 0000 0000 260, 241
SRLEN
SRCLK2 SRCLK1 SRCLK0
SRQEN
SRNQEN
SRPS
SRPR 0000 0000 260, 240
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 21.4 “Brown-out Reset (BOR)”.
The RA3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RA3 reads as ‘0’. This bit is
read-only.
 2010 Microchip Technology Inc.
Preliminary
DS41365D-page 41