PIC18F1XK22 Datasheet, PDF (133/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
13.4.8 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will con-
tinue to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from HFINTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
13.4.8.1 Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the RC_RUN Power-Managed
mode and the OSCFIF bit of the PIR2 register will be
set. The ECCP will then be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See the previous section for additional details.
13.4.9 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
TABLE 13-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
CCPR1H Capture/Compare/PWM Register 1, High Byte
259
CCPR1L Capture/Compare/PWM Register 1, Low Byte
259
CCP1CON P1M1
P1M0
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 259
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 259
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RABIE TMR0IF INT0IF RABIF
257
IPR1
—
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 260
IPR2
OSCFIP
C1IP
C2IP
EEIP
BCLIP
—
TMR3IP
—
260
PIE1
—
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 260
PIE2
OSCFIE
C1IE
C2IE
EEIE
BCLIE
—
TMR3IE
—
260
PIR1
—
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 260
PIR2
OSCFIF
C1IF
C2IF
EEIF
BCLIF
—
TMR3IF
—
260
PR2
Timer2 Period Register
258
PWM1CON PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
259
RCON
IPEN SBOREN
—
RI
TO
PD
POR
BOR
258
TMR1H Timer1 Register, High Byte
258
TMR1L
Timer1 Register, Low Byte
258
TMR2
Timer2 Register
258
TMR3H Timer3 Register, High Byte
259
TMR3L
Timer3 Register, Low Byte
259
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 260
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 258
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 258
T3CON
RD16
—
T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 259
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
 2010 Microchip Technology Inc.
Preliminary
DS41365D-page 133