PIC18F1XK22 Datasheet, PDF (354/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
TABLE 25-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
30 TMCL MCLR Pulse Width (low)
2
—
— s VDD = 3.3-5V, -40°C to +85°C
5
—
— s VDD = 3.3-5V
31
TWDT Standard Watchdog Timer Time-out 10
17
27 ms VDD = 3.3V-5V, -40°C to +85°C
Period (No Prescaler) ⁽⁵⁾
10
17
30 ms VDD = 3.3V-5V
31A TWDTLP Low Power Watchdog Timer
10
Time-out Period (No Prescaler)
10
32
TOST Oscillator Start-up Timer Period^{(1), (2)} —
18
18
1024
27 ms VDD = 3.3V-5V, -40°C to +85°C
33 ms VDD = 3.3V-5V
— Tosc (Note 3)
33* TPWRT Power-up Timer Period, PWRTE = 0 40
65 140 ms
34* TIOZ
I/O high-impedance from MCLR Low —
or Watchdog Timer Reset
— 2.0 s
35 VBOR Brown-out Reset Voltage
— 1.9 — V BORV = 1.9V
— 2.2 — V BORV = 2.2V
— 2.7 — V BORV = 2.7V
— 2.85 — V BORV = 2.85V
36* VHYST Brown-out Reset Hysteresis
25 50 75 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response
Time
1
3
5 s VDD  VBOR, -40°C to +85°C
10
VDD  VBOR
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
5: Design Target. If unable to meet this target, the maximum can be increased, but the minimum cannot be
changed.
DS41365D-page 354
Preliminary
 2010 Microchip Technology Inc.