PIC18F1XK22 Datasheet, PDF (83/388 Pages) Microchip Technology – 20-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC18F1XK22/LF1XK22
TABLE 8-1: PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0/CVREF/
VREF-/C1IN+/INT0/
PGD
RA0
AN0
0
O DIG LATA<0> data output.
1
I
TTL PORTA<0> data input; Programmable weak pull-up.
1
I ANA ADC channel 0 input.
CVREF
x
O ANA Comparator reference voltage output.
VREF-
1
I ANA ADC and Comparator voltage reference voltage (low) input.
C1IN+
1
I
DIG Comparator C1 non-inverting input.
INT0
PGD
1
I
ST External interrupt 0.
x
O DIG Serial execution data output for ICSP™.
RA1/AN1/C12IN0-/
VREF+/INT1/PGC
RA1
x
I
ST Serial execution data input for ICSP™.
0
O DIG LATA<1> data output.
1
I
TTL PORTA<1> data input; Programmable weak pull-up.
AN1
1
I ANA ADC channel 1.
C12IN0-
1
I ANA Comparator C1 and C2 non-inverting input channel 0.
VREF+
1
I ANA Comparator reference voltage (high) input ADC qual.
INT1
1
ST External interrupt 1.
PGC
x
O DIG Serial execution clock output for ICSP™.
RA2/AN2/C1OUT/
T0CKI/INT2/SRQ
RA2
x
I
ST Serial execution clock input for ICSP™.
0
O DIG LATA<2> data output.
1
I
TTL PORTA<2> data input; Programmable weak pull-up.
AN2
1
I ANA ADC channel 2.
C1OUT
0
O DIG Comparator C1 output.
T0CKI
1
I
ST Timer0 external clock input.
INT2
1
I
ST External interrupt 2.
SRQ
0
O DIG SR latch output.
RA3/MCLR/VPP
RA3
—⁽¹⁾
I
ST _{PORTA<37> data input; Programmable weak pull-up.}
MCLR
—
I
ST _{Active-low Master Clear with internal pull-up.}
VPP
—
I ANA High voltage programming input.
RA4/AN3/OSC2/
CLKOUT
RA4
0
O DIG LATA<4> data output.
1
I
TTL PORTA<4> data input; Programmable weak pull-up.
AN3
1
I
ANA _{A/D input channel 3.}
OSC2
x
O ANA _{Main oscillator feedback output connection (XT, HS and LP modes).}
CLKOUT
x
O DIG _{System instruction cycle clock output.}
RA5/OSC1/CLKIN/
T13CKI
RA5
0
O DIG LATA<5> data output.
1
I
TTL PORTA<5> data input; Programmable weak pull-up.
OSC1
x
I ANA Main oscillator input connection.
CLKIN
x
I ANA Main clock input connection.
T13CKI
1
I
ST _{Timer1 and Timer3 external clock input.}
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RA3 does not have a corresponding TRISA bit. This pin is always an input regardless of mode.
 2010 Microchip Technology Inc.
Preliminary
DS41365D-page 83