PIC18F67J11T-I Datasheet, PDF (86/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 6-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
CCPR4H
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx 65, 212
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx 65, 212
CCP4CON
—
—
DC4B1
DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 65, 212
CCPR5H
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx 65, 212
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx 65, 212
CCP5CON
—
—
DC5B1
DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 65, 212
SSP2BUF
MSSP2 Receive Buffer/Transmit Register
SSP2ADD/
SSP2MSK⁽⁵⁾
MSSP2 Address Register (I²C™ Slave mode), MSSP2 Baud Rate Reload Register (I²C Master mode)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
xxxx xxxx
0000 0000
0000 0000
65, 238,
248
65, 248
65, 255
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 65, 239,
249
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 65, 240,
250
SSP2CON2
GCEN
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN/
ACKSTAT ADMSK5⁽⁶⁾ ADMSK4⁽⁶⁾ ADMSK3⁽⁶⁾ ADMSK2⁽⁶⁾ ADMSK1⁽⁶⁾
SEN
SEN
0000 0000 65, 251,
283
CMSTAT
—
—
—
—
—
—
COUT2
COUT1 ---- --11 65, 321
PMADDRH/
CS2
CS1
Parallel Master Port Address High Byte
PMDOUT1H⁽⁹⁾ Parallel Port Out Data High Byte (Buffer 1)
0000 0000 66, 174
0000 0000 66, 177
PMADDRL/ Parallel Master Port Address Low Byte
PMDOUT1L⁽⁹⁾ Parallel Port Out Data Low Byte (Buffer 0)
0000 0000 66, 174
0000 0000 66, 174
PMDIN1H
Parallel Port In Data High Byte (Buffer 1)
0000 0000 66, 174
PMDIN1L
Parallel Port In Data Low Byte (Buffer 0)
0000 0000 66, 174
PMCONH
PMPEN
—
PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 0-00 0000 66, 168
PMCONL
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP 0000 0000 66, 169
PMMODEH
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16 MODE1
MODE0 0000 0000 66, 170
PMMODEL
WAITB1
WAITB0
WAITM3 WAITM2 WAITM1 WAITM0
WAITE1 WAITE0 0000 0000 66, 171
PMDOUT2H Parallel Port Out Data High Byte (Buffer 3)
0000 0000 66, 174
PMDOUT2L Parallel Port Out Data Low Byte (Buffer 2)
0000 0000 66, 174
PMDIN2H
Parallel Port In Data High Byte (Buffer 3)
0000 0000 66, 174
PMDIN2L
Parallel Port In Data Low Byte (Buffer 2)
0000 0000 66, 174
PMEH
PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10
PTEN9
PTEN8 0000 0000 66, 171
PMEL
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0 0000 0000 66, 172
PMSTATH
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F 00-- 0000 66, 172
PMSTATL
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E 10-- 1111 66, 173
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown; u = unchanged; — = unimplemented; q = value depends on condition; Bold = shared access SFRs
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address; available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I²C™ Slave mode. See Section 20.4.3.2
“Address Masking Modes” for details.
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 12.1.2 “Data Registers” for more information.
DS39778E-page 86
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