PIC18F67J11T-I Datasheet, PDF(235/466 Page) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

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PIC18F67J11T-I Datasheet, PDF (235/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

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PIC18F87J11 FAMILY

TABLE 19-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on Page:

INTCON

GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF INT0IF

RBIF

61

RCON

IPEN

â

CM

RI

TO

PD

POR

BOR

62

PIR1

PMPIF

ADIF

RC1IF

TX1IF SSP1IF CCP1IF TMR2IF TMR1IF

64

PIE1

PMPIE

ADIE

RC1IE

TX1IE SSP1IE CCP1IE TMR2IE TMR1IE

64

IPR1

PMPIP

ADIP

RC1IP

TX1IP SSP1IP CCP1IP TMR2IP TMR1IP

64

PIR2

OSCFIF CM2IF

CM1IF

â

BCL1IF LVDIF TMR3IF CCP2IF

64

PIE2

OSCFIE CM2IE

CM1IE

â

BCL1IE LVDIE TMR3IE CCP2IE

64

IPR2

OSCFIP CM2IP

CM1IP

â

BCL1IP LVDIP TMR3IP CCP2IP

64

PIR3

SSP2IF BCL2IF RC2IF

TX2IF TMR4IF CCP5IF CCP4IF CCP3IF

64

PIE3

SSP2IE BCL2IE RC2IE

TX2IE TMR4IE CCP5IE CCP4IE CCP3IE

64

IPR3

SSP2IP BCL2IP RC2IP

TX2IP TMR4IP CCP5IP CCP4IP CCP3IP

64

TRISB

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

64

TRISC

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

64

TRISE

TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0

64

TRISG

â

â

â

TRISG4 TRISG3 TRISG2 TRISG1 TRISG0

64

TRISH(1)

TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0

64

TMR1L(3)

Timer1 Register Low Byte

62

TMR1H(3) Timer1 Register High Byte

62

ODCON1(4)

â

â

â

CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD 62

T1CON(3)

RD16

T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

62

TMR2(3)

Timer2 Register

62

T2CON

PR2(3)

â

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

62

Timer2 Period Register

62

TMR3L

Timer3 Register Low Byte

65

TMR3H

Timer3 Register High Byte

65

T3CON

RD16

T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

65

TMR4

Timer4 Register

65

T4CON

PR4(3)

â

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0

65

Timer4 Period Register

65

CCPRxL(2) Capture/Compare/PWM Register x Low Byte

63

CCPRxH(2) Capture/Compare/PWM Register x High Byte

63,

CCPxCON(2)

PxM1

PxM0

DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

63

ECCPxAS(2) ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0

63

ECCPxDEL(2) PxRSEN PxDC6

PxDC5

PxDC4

PxDC3

PxDC2

PxDC1

PxDC0

63

Legend:

Note 1:

2:

3:

4:

â = unimplemented, read as â0â. Shaded cells are not used during ECCP operation.

This register is available on 80-pin devices only.

Generic term for all of the identical registers of this name for all Enhanced CCP modules, where âxâ identifies the

individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same

generic name are identical.

Default (legacy) SFR at this address, available when WDTCON<4> = 0.

Configuration SFR, overlaps with the default SFR at this address; available only when WDTCON<4> = 1.

ï£ 2007-2012 Microchip Technology Inc.

DS39778E-page 235

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