PIC18F67J11T-I Datasheet, PDF (182/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
12.3.5 CHIP SELECT FEATURES
Up to two chip select lines, PMCS1 and PMCS2, are
available for the Master modes of the PMP. The two chip
select lines are multiplexed with the Most Significant bits
of the address bus (PMADDRH<6> and PMADDRH<7>).
When a pin is configured as a chip select, it is not included
in any address auto-increment/decrement. The function
of the chip select signals is configured using the chip
select function bits (PMCONL <7:6>).
12.3.6 AUTO-INCREMENT/DECREMENT
While the module is operating in one of the Master
modes, the INCMx bits (PMMODEH<3:4>) control the
behavior of the address value. The address can be
made to automatically increment or decrement after
each read and write operation. The address increments
once each operation is completed and the BUSY bit
goes to ‘0’. If the chip select signals are disabled and
configured as address bits, the bits will participate in
the increment and decrement operations; otherwise,
the CS2 and CS1 bit values will be unaffected.
12.3.7 WAIT STATES
In Master mode, the user has control over the duration
of the read, write and address cycles by configuring the
module Wait states. Three portions of the cycle, the
beginning, middle, and end, are configured using the
corresponding WAITBx, WAITMx and WAITEx bits in
the PMMODEL register.
The WAITB<1:0> bits (PMMODEL<7:6>) set the
number of Wait cycles for the data setup prior to the
PMRD/PMWT strobe in Mode 10 or prior to the
PMENB strobe in Mode 11. The WAITM<3:0> bits
(PMMODEL<5:2>) set the number of Wait cycles for the
PMRD/PMWT strobe in Mode 10 or for the PMENB
strobe in Mode 11. When this Wait state setting is 0, then
WAITBx and WAITEx have no effect. The WAITE<1:0>
bits (PMMODEL<1:0>) define the number of Wait cycles
for the data hold time, after the PMRD/PMWT strobe in
Mode 10, or after the PMENB strobe in Mode 11.
12.3.8 READ OPERATION
To perform a read on the Parallel Master Port, the user
reads the PMDIN1L register. This causes the PMP to
output the desired values on the chip select lines and
the address bus. Then the read line (PMRD) is strobed.
The read data is placed into the PMDIN1L register.
If the 16-bit mode is enabled (MODE16 = 1), the read
of the low byte of the PMDIN1L register will initiate two
bus reads. The first read data byte is placed into the
PMDIN1L register, and the second read data is placed
into the PMDIN1H.
Note that the read data obtained from the PMDIN1L
register is actually the read value from the previous
read operation. Hence, the first user read will be a
dummy read to initiate the first bus read and fill the read
register. Also, the requested read value will not be
ready until after the BUSY bit is observed low. Thus, in
a back-to-back read operation, the data read from the
register will be the same for both reads. The next read
of the register will yield the new value.
12.3.9 WRITE OPERATION
To perform a write onto the parallel bus, the user writes
to the PMDIN1L register. This causes the module to
first output the desired values on the chip select lines
and the address bus. The write data from the PMDIN1L
register is placed onto the PMD<7:0> data bus. Then
the write line (PMWR) is strobed. If the 16-bit mode is
enabled (MODE16 = 1), the write to the PMDIN1L reg-
ister will initiate two bus writes. First write will consist of
the data contained in PMDIN1L and the second write
will contain the PMDIN1H.
12.3.10 PARALLEL MASTER PORT STATUS
12.3.10.1 The BUSY Bit
In addition to the PMP interrupt, a BUSY bit is provided
to indicate the status of the module. This bit is only
used in Master mode. While any read or write operation
is in progress, the BUSY bit is set for all but the very last
CPU cycle of the operation. In effect, if a single-cycle
read or write operation is requested, the BUSY bit will
never be active. This allows back-to-back transfers.
While the bit is set, any request by the user to initiate a
new operation will be ignored (i.e., writing or reading
the lower byte of the PMDIN1L register will not initiate
either a read nor a write).
12.3.10.2 INTERRUPTS
When the PMP module interrupt is enabled for Master
mode, the module will interrupt on every completed
read or write cycle; otherwise, the BUSY bit is available
to query the status of the module.
DS39778E-page 182
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