PIC18F67J11T-I Datasheet, PDF (144/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
TABLE 11-6: PORTB FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/INT0/FLT0 RB0
0
O DIG LATB<0> data output.
1
I
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
INT0
1
I
ST External Interrupt 0 input.
FLT0
1
I
ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
RB1/INT1/
PMA4
RB1
0
O DIG LATB<1> data output.
1
I
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
INT1
1
I
ST External Interrupt 1 input.
PMA4
x
O
— Parallel Master Port address out.
RB2/INT2/
PMA3
RB2
0
O DIG LATB<2> data output.
1
I
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
INT2
1
I
ST External Interrupt 2 input.
PMA3
x
O
— Parallel Master Port address out.
RB3/INT3/
PMA2/ECCP2/
P2A
RB3
INT3
0
O DIG LATB<3> data output.
1
I
TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
1
I
ST External Interrupt 3 input.
PMA2
x
ECCP2⁽¹⁾
0
O
— Parallel Master Port address out.
O DIG ECCP2 compare output and CCP2 PWM output; takes priority over port
data.
1
I
ST ECCP2 capture input.
P2A⁽¹⁾
0
O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
RB4/KBI0/
PMA1
RB4
0
O DIG LATB<4> data output.
1
I
TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
KBI0
I
TTL Interrupt-on-pin change.
PMA1
x
O
— Parallel Master Port address out.
RB5/KBI1/
PMA0
RB5
0
O DIG LATB<5> data output.
1
I
TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1
I
TTL Interrupt-on-pin change.
PMA0
x
O
— Parallel Master Port address out.
RB6/KBI2/PGC RB6
0
O DIG LATB<6> data output.
1
I
TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2
1
I
TTL Interrupt-on-pin change.
PGC
x
I
ST Serial execution (ICSP™) clock input for ICSP and ICD operation.⁽²⁾
RB7/KBI3/PGD RB7
0
O DIG LATB<7> data output.
1
I
TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3
PGD
1
I
TTL Interrupt-on-pin change.
x
O DIG Serial execution data output for ICSP and ICD operation.⁽²⁾
x
I
ST Serial execution data input for ICSP and ICD operation.⁽²⁾
Legend:
Note 1:
2:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only); the default assignment is RC1.
All other pin functions are disabled when ICSP™ or ICD is enabled.
DS39778E-page 144
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