PIC18F67J11T-I Datasheet, PDF (42/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
3.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
Clock from
Ext. System
FOSC/4
OSC1/CLKI
PIC18F87J11
OSC2/CLKO
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
Clock from
Ext. System
Open
OSC1
PIC18F87J11
(HS Mode)
OSC2
3.4.3 PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency oscil-
lator circuit, or to clock the device up to its highest rated
frequency from a crystal oscillator. This may be useful for
customers who are concerned with the External Memory
Interface (EMI) due to high-frequency crystals, or users
who require higher clock speeds from an internal
oscillator.
3.4.3.1 HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external
oscillating source to produce frequencies up to
40 MHz.
The PLL is enabled by programming the FOSC<2:0>
Configuration bits to either ‘111’ (for ECPLL) or ‘101’ (for
HSPLL). In addition, the PLLEN bit (OSCTUNE<6>)
must also be set. Clearing PLLEN disables the PLL,
regardless of the chosen oscillator configuration. It also
allows additional flexibility for controlling the applica-
tion’s clock speed in software.
FIGURE 3-5:
PLL BLOCK DIAGRAM
HSPLL or ECPLL (CONFIG2L)
PLL Enable (OSCTUNE)
OSC2
HS or EC
OSC1 Mode
FIN
FOUT
Phase
Comparator
Loop
Filter
4
VCO
SYSCLK
3.4.3.2 PLL and INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
described in Section 3.5.2 “INTPLL Modes”.
DS39778E-page 42
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