PIC18F67J11T-I Datasheet, PDF (214/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
18.3 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remains unchanged (that is, reflects the state of
the I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM<3:0>). At the same time, the
interrupt flag bit, CCPxIF, is set.
18.3.1 CCP PIN CONFIGURATION
The user must configure the CCP pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP5CON register will force
the RG4 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
18.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
18.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the corresponding CCP pin is
not affected. Only a CCP interrupt is generated, if
enabled, and the CCPxIE bit is set.
FIGURE 18-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR4H CCPR4L
Set CCP4IF
CCP4 Pin
Comparator
Compare
Match
Output
Logic
4
CCP4CON<3:0>
SQ
R
TRIS
Output Enable
0
TMR1H TMR1L
0
1
TMR3H TMR3L
1
T3CCP1
T3CCP2
Set CCP5IF
CCP5 Pin
Comparator
Compare
Match
CCPR5H CCPR5L
Output
Logic
4
CCP5CON<3:0>
SQ
R
TRIS
Output Enable
DS39778E-page 214
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