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| PIC18F67J11T-I Datasheet, PDF (163/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers | |||
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PIC18F87J11 FAMILY
TABLE 11-18: PORTH FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RH7/PMWR/
AN15/P1B
RH7
0
O DIG LATH<7> data output.
1
I
ST PORTH<7> data input.
PMWR(2)
x
O DIG Parallel Master Port write strobe.
x
I
TTL Parallel Master Port write in.
AN15
I ANA A/D input channel 15. Default input configuration on POR; does not affect
digital output.
P1B(1)
0
O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Donât care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignments for P1B/P1C and P3B/P3C when the ECCPMX Configuration bit is cleared. Default assignments
are PORTE<6:3>.
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
TABLE 11-19: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
PORTH(1)
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
64
LATH(1)
LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0
65
TRISH(1)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0
64
ANCON1(2) PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
63
Legend: Shaded cells are not used by PORTH.
Note 1: Unimplemented on 64-pin devices, read as â0â.
2: Configuration SFR, overlaps with the default SFR at this address; available only when WDTCON<4> = 1.
ï£ 2007-2012 Microchip Technology Inc.
DS39778E-page 163
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