PIC18F67J11T-I Datasheet, PDF (174/466 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers

PIC18F87J11 FAMILY
12.1.2 DATA REGISTERS
The PMP module uses 6 registers for transferring data
into and out of the microcontroller. They are arranged
as three pairs to allow the option of 16-bit data
operations:
• PMDIN1H and PMDIN1L
• PMDIN2H and PMDIN2L
• PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L
• PMDOUT2H and PMDOUT2L
The PMDIN1 register is used for incoming data in Slave
modes, and both input and output data in Master
modes. The PMDIN2 register is used for buffering input
data in select Slave modes.
The PMADDRx/PMDOUT1x registers are actually a
single register pair; the name and function is dictated
by the module’s operating mode. In Master modes, the
registers functions as the PMADDRH and PMADDRL
registers, and contain the address of any incoming or
outgoing data. In Slave modes, the registers function
as PMDOUT1H and PMDOUT1L and are used for
outgoing data.
PMADDRH differs from PMADDRL in that it can also
have limited PMP control functions. When the module
is operating in select Master mode configurations, the
upper two bits of the register can be used to determine
the operation of chip select signals. If chip select
signals are not used, PMADDR simply functions to hold
the upper 8 bits of the address. The function of the
individual bits in PMADDRH is shown in Register 12-9.
The PMDOUT2H and PMDOUT2L registers are only
used in buffered Slave modes and serve as a buffer for
outgoing data.
12.1.3
PAD CONFIGURATION CONTROL
REGISTER
In addition to the module level configuration options,
the PMP module can also be configured at the I/O pin
for electrical operation. This option allows users to
select either the normal Schmitt Trigger input buffer on
digital I/O pins shared with the PMP, or use TTL level
compatible buffers instead. Buffer configuration is
controlled by the PMPTTL bit in the PADCFG1 register.
The PADCFG1 register is one of the shared address
SFRs, and has the same address as the TMR2 regis-
ter. PADCFG1 is accessed by setting the ADSHR bit
(WDTCON<4>). Refer to Section 6.3.4.1 “Shared
Address SFRs” for more information.
REGISTER 12-9: PMADDRH: PARALLEL PORT ADDRESS REGISTER, HIGH BYTE
(MASTER MODES ONLY)⁽¹⁾
R/W-0
CS2
bit 7
R/W-0
CS1
R/W-0
ADDR13
R/W-0
ADDR12
R/W-0
ADDR11
R/W-0
ADDR10
R/W-0
ADDR9
R/W-0
ADDR8
bit 0
Legend:
R = Readable bit
-n = Value at Reset
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
x = bit is unknown
bit 7
bit 6
bit 5-0
CS2: Chip Select 2 bit
If PMCON<7:6> = 10 or 01:
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
If PMCON<7:6> = 11 or 00:
Bit functions as ADDR<15>.
CS1: Chip Select 1 bit
If PMCON<7:6> = 10:
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
If PMCON<7:6> = 11 or 0x:
Bit functions as ADDR<14>.
ADDR<13:8>: Destination Address bits
Note 1: In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers.
DS39778E-page 174
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